Non-volatile memory with source line resistance compensation
US10984872B1 · kind B1 · utility
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5References
20Claims
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Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.