Semiconductor package
US10985091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15173
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.