Chip packaging method and chip packaging structure
US10985120B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Sep 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a chip packaging method and a chip packaging structure. The passivation layer is arranged on the pads of the wafer, then the first bonding layer is formed on the passivation layer, and the second bonding layer is formed on the substrate. The substrate and the wafer are bonded and packaged together by bonding the first bonding layer and the second bonding layer. The pads are only used as a conductive structure, not as a bonding layer due to the passivation layer arranged between the pads and the bonding layer. The through silicon via is arranged at the position above the pad and avoiding the bonding layer, so as to connect the functional circuit region between the wafer and the substrate to the outside of the chip packaging structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.