Bump structure and fabricating method thereof
US10985121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.