Fractional divider
US10985761B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jun 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional divider is described herein which effectively performs an integer division followed by phase shifting, pulse swallowing, and/or multiplexing to realize a fractional divisor. The fractional divider divides an input clocking signal by a first integer divisor in a first mode of operation or by a second integer divisor in a second mode of operation to provide a first phase of a divided digital signal. Thereafter, the fractional divider shifts the first phase of the divided digital signal to provide a second phase of the divided digital signal in the first and second modes of operation. Finally, the fractional divider synchronizes an output clocking signal to the first phase of the divided digital signal and the second phase of the divided digital signal in the first and second modes of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.