Mechanism for interrupting and resuming execution on an unprotected pipeline processor
US10990398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Apr 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.