Handling asynchronous power loss in a memory sub-system that programs sequentially
US10990526B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a NVM memory, and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone state and to a zone index; a journal data structure (JDS); and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index, wherein the zone write pointer includes a location in the LBA space; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; update, within the JDS, metadata of the entry of one the ZMDS or the JDS affected by a flush transition between the ZMDS and the HFUT; and in response to an asynchronous power loss event, flush the JDS and the HFUT to a NVM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.