Scan channel fabric for tiled circuit designs
US10990739B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Jul 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/4912
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes multiple circuit tiles disposed in a tiled arrangement in a circuit block between a first boundary and a second boundary. Each circuit tile is an instance of a circuit cell having a first edge and a second edge. The circuit cell has a scan channel circuit that includes a configurable scan channel switch and scan channels extending between the first edge and the second edge of the circuit cell through the configurable scan channel switch. Respective scan channels in the multiple circuit tiles are joined together and extend between the first boundary and the second boundary of the block of tiled arrangement. Each circuit tile can be configured to receive scan-in test data through a scan channel from either the first boundary or the second boundary, and to output scan-out result data of the circuit tile through a scan channel to either the first boundary or the second boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.