Semiconductor device including distributed write driving arrangement and method of operating same
US10991420B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2020 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Aug 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.