Complementary dual-modular redundancy memory cell
US10991421B2 · kind B2 · utility
0Cited by
0References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Oct 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.