Method of forming protection layer in FinFET device
US10991629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fin-based transistor and method for making same. In some embodiments, the transistor includes a first fin and a second fin formed on a substrate, the first and second fins being laterally spaced from each other, wherein an upper portion of the first fin is doped with a first type of dopant and an upper portion of the second fin is doped with a second type of dopant different from the first type of dopant; a protection layer formed over the first and second fins, wherein the protection layer comprises a dielectric material selected from a group comprising: silicon nitride, silicon oxynitride, and a combination thereof; and source and drain features formed in respective side portions of the first and second fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.