Jen-Chun Chou
4Patents
1h-index
5Co-inventors
33Inventor score
Filing activity: Oct 4, 2017 → Nov 8, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10468309B2 | Method of forming protection layer in FinFET device | Electricity | 1 | Active |
| US10991629B2 | Method of forming protection layer in FinFET device | Electricity | 0 | Active |
| US12283526B2 | Edge fin trim process | Electricity | 0 | Active |
| US11424165B2 | Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.