System and method for testing voltage monitors
US10996266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2856
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.