Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address
US10997080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Feb 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for address table cache management, a first logical address associated with a first read command may be received. The first logical address may be associated with a first segment of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second segment of the address mapping table. A correlation metric associating the first segment to the second segment may be increased in response to receiving the first logical address before the second logical address. The first logical address and second logical address may each map to a physical address within the address mapping table, and a mapping table cache may be configured to store two or more segments. The mapping table cache may then be managed based on the correlation metric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.