Enabling high speed command address interface for random read
US10997097B2 · kind B2 · utility
1Cited by
11References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 4, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jul 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.