Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification
US10997339B2 · kind B2 · utility
0Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2017 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Sep 5, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.