John Stuart Freeman
15Patents
4h-index
16Co-inventors
53Inventor score
Filing activity: Oct 12, 2006 → May 3, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10599404B1 | M/A for compiling parallel program having barrier synchronization for programmable hardware | Physics | 11 | Active |
| US9166597B1 | Integrated circuit processing via offload processor | Electricity | 7 | Active |
| US8201114B1 | Method and apparatus for performing look up table unpacking and repacking for resynthesis | Physics | 7 | Active |
| US9117022B1 | Hierarchical arbitration | Physics | 6 | Active |
| US9922150B1 | Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool | Physics | 4 | Active |
| US9424043B1 | Forward-flow selection | Physics | 2 | Active |
| US7720243B2 | Acoustic enhancement for behind the ear communication devices | Electricity | 2 | Active |
| US9703696B1 | Guided memory buffer allocation | Physics | 1 | Active |
| US9547738B1 | Invariant code optimization in high-level FPGA synthesis | Physics | 1 | Active |
| US10120969B1 | Global variable optimization for integrated circuit applications | Physics | 1 | Active |
| US10997339B2 | Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification | Physics | 0 | Active |
| US9135087B1 | Workgroup handling in pipelined circuits | Physics | 0 | Active |
| US10437743B1 | Interface circuitry for parallel computing architecture circuits | Emerging Cross-Sectional Technologies | 0 | Active |
| US12393756B2 | Methods and apparatus for profile-guided optimization of integrated circuits | Physics | 0 | Active |
| US11675948B2 | Methods and apparatus for profile-guided optimization of integrated circuits | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.