Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
US10997510B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing a tanh and/or sigmoid operation/function. The inline post processing unit is further configured to accept data from a set of registers configured to maintain output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the tanh and/or sigmoid operation on each element of the data from the processing block on a per-element basis via the one or more lookup tables, and stream post processing result of the per-element tanh and/or sigmoid operation back to the OCM after the tanh and/or sigmoid operation is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.