Method for enhancing tunnel magnetoresistance in memory device
US10998024B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 2, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Mar 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.