RRAM write using a ramp control circuit
US10998044B2 · kind B2 · utility
2Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2017 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.