Memory system capable of reducing the reading time
US10998059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jul 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bias circuit includes a charging current reproduce unit, a cell current reproduce unit, a current comparator, and a bit line bias generator. The charging current reproduce unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduce unit generates a cell reference voltage according to a cell current flowing through a common source transistor. The current comparator includes a first current generator for generating a replica charging current according to the charging reference voltage, and a second current generator for generating a replica cell current according to the cell reference voltage. The bit line bias generator generates a bit line bias voltage to control a page buffer for charging a bit line according to a difference between the replica charging current and the replica cell current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.