Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device
US10998378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/231
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.