Philippe Boivin
51Patents
3h-index
33Co-inventors
66Inventor score
Filing activity: Dec 14, 1988 → Apr 25, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4997777A | Manufacturing process for an integrated circuit comprising double gate components | Electricity | 21 | Expired |
| US9929146B2 | Method of forming MOS and bipolar transistors | Electricity | 4 | Active |
| US10128314B2 | Vertical bipolar transistor | Electricity | 3 | Active |
| US8048685B2 | Magnetic RAM | Electricity | 2 | Active |
| US11653582B2 | Chip containing an onboard non-volatile memory comprising a phase-change material | Physics | 2 | Active |
| US9196654B2 | Method of fabricating a vertical MOS transistor | Electricity | 2 | Active |
| US7315071B2 | Magnetic RAM | Electricity | 2 | Expired |
| US9559297B2 | Vertical transistor for resistive memory | Electricity | 2 | Active |
| US8853615B2 | Ultraviolet radiation measurement sensor | Physics | 1 | Active |
| US9793321B2 | Resistive memory cell having a compact structure | Electricity | 1 | Active |
| US9735353B2 | Phase-change memory cell having a compact structure | Physics | 1 | Active |
| US10714501B2 | Co-integration of bulk and SOI transistors | Electricity | 1 | Active |
| US8680603B2 | Transistor comprising nanocrystals and related devices | Electricity | 1 | Active |
| US11875847B2 | Self-referenced and regulated sensing solution for phase change memory with ovonic threshold switch | Physics | 1 | Active |
| US11411177B2 | Phase-change memory with insulated walls | Electricity | 1 | Active |
| US11957067B2 | Phase-change memory cell having a compact structure | Physics | 1 | Active |
| US10431630B2 | Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device | Electricity | 1 | Active |
| US12342734B2 | Phase-change memory | Electricity | 0 | Active |
| US8921219B2 | Process for fabricating a transistor comprising nanocrystals | Electricity | 0 | Active |
| US6590256B2 | EEPROM cell testing circuit | Physics | 0 | Expired |
| US11114614B2 | Process for fabricating resistive memory cells | Electricity | 0 | Active |
| US8999796B2 | Manufacturing process of memory cells | Electricity | 0 | Active |
| US8830761B2 | Method of reading and writing nonvolatile memory cells | Physics | 0 | Active |
| US9941390B2 | Method of fabricating a vertical MOS transistor | Electricity | 0 | Active |
| US11211428B2 | Integrated circuit including transistors having a common base | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.