Polishing pad that minimizes occurrence of defects and process for preparing the same
US11000935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Feb 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.