Gate contact over active processes

US11004687B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Gaurav Thareja · Santa Clara, US
• Keyvan Kashefizadeh · Dublin, US
• Xikun Wang · Sunnyvale, US
• Anchuan Wang · San Jose, US
• Sanjay Natarajan · Portland, US
• Sean M. Seutter · Fremont, US
• Dong Wu · Carlsbad, US

Key dates

• Filing date: Jun 17, 2019
• Grant date: May 11, 2021
• Expiry date: Jun 17, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76883
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.