Method of forming a FinFET device with gaps in the source/drain region
US11004725B2 · kind B2 · utility
1Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.