Semiconductor package having symmetrically arranged power terminals and method for producing the same

US11004764B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Juergen Hoegerl · Regensburg, DE
• Tao Hong · Beijing, CN
• Tino Karczewski · Sinzing, DE
• Matthias Lassmann · Lippstadt, DE
• Christian Schweikert · Munich, DE

Key dates

• Filing date: Jul 23, 2019
• Grant date: May 11, 2021
• Expiry date: Jul 23, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8325
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.