Operating method of an electrically erasable programmable read only memory (EEPROM) cell
US11004857B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Feb 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.