Semiconductor device and manufacturing method thereof
US11004937B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a gate structure, a source/drain region, a contact opening, an etching stop layer, an interlayer dielectric layer, and a first contact structure. The substrate includes a buried insulation layer, a semiconductor layer, and an isolation structure. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The isolation structure and the source/drain region are disposed in the semiconductor layer. The contact opening penetrates at least a part of the substrate. The etching stop layer is disposed on the gate structure, the source/drain region, a sidewall of the contact opening, and a bottom of the contact opening. The interlayer dielectric layer is disposed on the etching stop layer. The first contact structure penetrates the interlayer dielectric layer and the etching stop layer in the contact opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.