Techniques for MRAM MTJ top electrode to metal layer interface including spacer
US11005032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.