Delay line circuit
US11005464B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2020 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a delay line circuit including an output stage. The output stage includes a first inverter cell, a second inverter cell, a correction circuit, and a first switch capacitor array. The input terminal of the first inverter cell receives a reference clock signal. The input terminal of the second inverter cell is coupled with the output terminal of the first inverter cell. The first terminal of the correction circuit is coupled with the output terminal of the first inverter cell, and the second terminal of the correction circuit is coupled with a ground, wherein the correction circuit corrects a duty cycle of the delay line circuit. The first terminal of the first switch capacitor array is coupled with the output terminal of the second inverter cell, and the second terminal of the first switch capacitor array is coupled with the ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.