LDPC decoder, semiconductor memory system, and operating method thereof
US11005499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.