Processing core with data associative adaptive rounding
US11010132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing cores with data associative adaptive rounding and associated methods are disclosed herein. One disclosed processing core comprises an arithmetic logic unit cluster configured to generate a value for a unit of directed graph data using input directed graph data, a comparator coupled to a threshold register and a data register, a core controller configured to load a threshold value into the threshold register when the value for the unit of directed graph data is loaded into the data register, and a rounding circuit. The rounding circuit is configured to receive the value for the unit of directed graph data from the arithmetic logic unit cluster and conditionally round the value for the unit of directed graph data based on a comparator output from the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.