Alex Cejkov
11Patents
1h-index
9Co-inventors
39Inventor score
Filing activity: Jun 6, 2019 → Jun 18, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10644721B2 | Processing core data compression and storage system | Electricity | 1 | Active |
| US11010132B2 | Processing core with data associative adaptive rounding | Physics | 1 | Active |
| US12118060B2 | Computational circuit with hierarchical accumulator | Physics | 0 | Active |
| US11520701B2 | Data structure optimized dedicated memory caches | Physics | 0 | Active |
| US12340185B2 | Processing core with data associative adaptive rounding | Physics | 0 | Active |
| US12248430B2 | Overlay layer for network of processor cores | Physics | 0 | Active |
| US10938413B2 | Processing core data compression and storage system | Electricity | 0 | Active |
| US11645041B2 | Processing core with data associative adaptive rounding | Physics | 0 | Active |
| US12039289B2 | Processing core with data associative adaptive rounding | Physics | 0 | Active |
| US12321855B2 | Graph execution using access request response dynamic batch assembly | Physics | 0 | Active |
| US12019546B2 | Data structure optimized dedicated memory caches | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.