Instruction window centric processor simulation
US11010182B2 · kind B2 · utility
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Key dates
| Filing date | Jun 17, 2013 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for simulating a set of instructions to be executed on a processor including performing a performance simulation of the processor over a number of simulation cycles. Modeling, in a frontend component, branch prediction and instruction cache is performed providing instructions to the instruction window, and modeling of an instruction window for the cycle is performed. From the simulation, a performance parameter of the processor is obtained without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.