Memory device for adjusting memory capacity per channel and memory system including the same
US11010316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2018 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.