NOC peripheral interconnect interrogation scheme
US11010322B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Dec 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the plurality of switches or an NPI protocol block of the plurality of NPI protocol blocks generate a response message for a service command query with the destination address associated with the intended circuit block that is received from the master instead of routing the service command query to the intended circuit block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.