Knowledge-based analog layout generator
US11010528B2 · kind B2 · utility
1Cited by
5References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 12, 2016 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.