Semiconductor memory device including parallel substrates in three dimensional structures
US11011208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Oct 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.