Memory device and operation method thereof
US11011230B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2020 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array, a first reference unit, a second reference unit, and a control unit. The memory array includes a plurality of memory cells. The first reference unit provides a first reference current. The second reference unit provides a second reference current, wherein a current value of the first reference current is less than a current value of the second reference current. In a data-writing operation, the control unit provides a first current to a memory cell, reads a second current generated by the memory cell in response to the first current, and selects to compare the second current with the first reference current or to compare the second current with the second reference current according to a data-writing state of the memory cell, so as to determine whether a data writing of the data writing state is successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.