Engineered substrate structures for power and RF applications
US11011373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2020 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Apr 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/801
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.