Method for forming circuit board stacked structure
US11013103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jul 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/041
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.