Instruction and logic for parallel multi-step power management flow
US11016556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Jul 16, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.