Dean Mulla
47Patents
16h-index
93Co-inventors
84Inventor score
Filing activity: Aug 4, 1994 → Sep 26, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6948094B2 | Method of correcting a machine check error | Physics | 261 | Expired |
| US6185660A | Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss | Physics | 77 | Expired |
| US5652859A | Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues | Physics | 65 | Expired |
| US5664148A | Cache arrangement including coalescing buffer queue for non-cacheable data | Physics | 51 | Expired |
| US5577227A | Method for decreasing penalty resulting from a cache miss in multi-level cache system | Physics | 45 | Expired |
| US6772383B1 | Combined tag and data ECC for enhanced soft error recovery from cache tag errors | Electricity | 37 | Expired |
| US6418521B1 | Hierarchical fully-associative-translation lookaside buffer structure | Physics | 36 | Expired |
| US6427188B1 | Method and system for early tag accesses for lower-level caches in parallel with first-level cache | Emerging Cross-Sectional Technologies | 35 | Expired |
| US6539457B1 | Cache address conflict mechanism without store buffers | Physics | 28 | Expired |
| US6272597A | Dual-ported, pipelined, two level cache system | Physics | 27 | Expired |
| US5860095A | Conflict cache having cache miscounters for a computer memory system | Physics | 25 | Expired |
| US6105115A | Method and apparatus for managing a memory array | Physics | 20 | Expired |
| US6557078B1 | Cache chain structure to implement high bandwidth low latency cache memory subsystem | Physics | 19 | Expired |
| US6687262B1 | Distributed MUX scheme for bi-endian rotator circuit | Physics | 18 | Expired |
| US6226763A | Method and apparatus for performing cache accesses | Physics | 18 | Expired |
| US5870387A | Method and apparatus for initializing a ring | Physics | 17 | Expired |
| US6507892B1 | L1 cache memory | Physics | 15 | Expired |
| US5696939A | Apparatus and method using a semaphore buffer for semaphore instructions | Physics | 14 | Expired |
| US7159046B2 | Method and apparatus for configuring communication between devices in a computer system | Physics | 13 | Expired |
| US7376877B2 | Combined tag and data ECC for enhanced soft error recovery from cache tag errors | Electricity | 12 | Expired |
| US6427189B1 | Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline | Physics | 11 | Expired |
| US6381678B2 | Processing ordered data requests to a memory | Physics | 10 | Expired |
| US6591393B1 | Masking error detection/correction latency in multilevel cache transfers | Physics | 9 | Expired |
| US6453427B2 | Method and apparatus for handling data errors in a computer system | Physics | 8 | Expired |
| US6427191B1 | High performance fully dual-ported, pipelined cache design | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.