Neural network operation reordering for parallel execution
US11016775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Aug 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for reordering operations of a neural network to improve runtime efficiency. In some examples, a compiler receives a description of the neural network comprising a plurality of operations. The compiler may determine which execution engine of a plurality of execution engines is to perform each of the plurality of operations. The compiler may determine an order of performance associated with the plurality of operations. The compiler may identify a runtime inefficiency based on the order of performance and a hardware usage for each of the plurality of operations. An operation may be reordered to reduce the runtime inefficiency. Instructions may be compiled based on the plurality of operations, which include the reordered operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.