Directed interrupt virtualization with interrupt table
US11016800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Feb 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory operationally connected with the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.