Methods and apparatuses of configurable integrated circuits
US11017142B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Sep 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.