Patent · US Active

System and method for repeating a synchronized set of layout geometries

US11017145B1 · kind B1 · utility

0Cited by

7References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ashwani Kumar Sanwal · Bhor, IN
Vandana Gupta · Delhi, IN
Devendra Deshpande · Noida, IN

Key dates

Filing date	Dec 4, 2019
Grant date	May 25, 2021
Priority date	—
Expiry date	Dec 4, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.