Patent · US Active

Static random-access memory (SRAM) system with delay tuning and control and a method thereof

US11017848B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

Ambuj Jain · Bengaluru, IN
Akash GUPTA · Bengaluru, IN
Manish Chandra Joshi · Bengaluru, IN
Parvinder Kumar Rana · Bengaluru, IN
Abhishek Kesarwani · Bengaluru, IN

Key dates

Filing date	Dec 19, 2019
Grant date	May 25, 2021
Priority date	—
Expiry date	Dec 19, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.