Interposer, semiconductor package, and method of fabricating interposer
US11018026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0588
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.